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DS33Z41DK
CONTROL REGISTERS
Register Name: delay_line1, delay_line2, delay_line3, delay_line4
Register Description: DS33Z41 frame delay
Register Offset: 0X4001, 0X4002, 0X4003, 0X4004
Bit #
Name
Default
7
—
—
6
—
—
5
B5
—
4
B4
—
3
B3
0
2
B2
0
1
B1
0
0
B0
0
Bits 5 to 0: B5 to B0. Number of frame delay for a given line.
Register Name: MO+CLK
Register Description: DS33ZXY Mode and Clock Settings
Register Offset: 0X4005
Bit #
Name
Default
7
LB
0
6
MC
—
5
IR
—
4
tgapclk
1
3
rgapclk
1
2
comm_tclk
0
1
common_rclk
0
0
z41_mode
0
Bit 7: LB
0 = Normal operation, traffic goes from the Z chip through the FPGA and to the DS21458.
1 = Loopback, Z chip rser is driven by Z chip tser. Clocks, and frame sync for Z41, are still driven by DS21458.
Bit 6: INVERT_RCLKh
0 = Do not invert RCLK.
1 = Invert RCLK.
Bit 5: MclkHiBpclkLow
0 = Use BPCLK for clock signals below.
1 = Use MCLK for clock signals below.
This signal drives the following clocks: TCLK (when bit for common_tclk is set); RCLK (when bit for common_rclk is
set); TSYSCLK and RSYSCLK (when bit for Z41_mode is set).
Bit 4: TGAPCLK
0 = Drive internal TGAPCLKx signal with TCLKx.
1 = Drive internal TGAPCLKx signal with TGAPCLK pin.
Bit 3: RGAPCLK
0 = Drive internal RGAPCLKx signal with RCLKx.
1 = Drive internal RGAPCLKx signal with RGAPCLK pin.
Bit 2: Common TCLK
0 = Drive TCLKx with internal TGAPCLKx signal (see bit 4)
1 = Drive Z chip TCLKx with BPCLK
Bit 1: Common RCLK
0 = Drive RCLKx with internal RGAPCLKx signal (see bit 3).
1 = Drive Z chip RCLKx with BPCLK.
Bit 0: Z41 Mode
0 = Not in Z41 mode.
1 = In Z41 mode.
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